Control circuitry for electronic musical instrument

ABSTRACT

In an electronic musical instrument of the type including a keyboard and a resistor voltage divider having points there along respectively coupled by way of actuable keys associated with the keyboard to a single output bus, there is provided improved control electronics having output signals that control, for example, an envelope generator and a voltage controlled oscillator. The control electronics includes an oscillator and gate circuit coupled to the bus for providing a gate output signal which is present as long as at least one key is actuated, a sample/hold circuit coupled to the bus for providing a control voltage signal the amplitude of which is a function of the position of the actuated key, and a trigger signal means coupled to the keyboard and responsive to the gate circuit and the actuation of two or more keys for providing a trigger signal of shorter duration than the gate signal and occurring near the commencement of the gate signal.

United States Patent 1191 Colin CONTROL CIRCUITRY FOR ELECTRONIC MUSICALINSTRUMENT Prirnary Examiner-Richard B. Wilkinson [75] Inventor: DennisP. Colin, Beverly, Mass. Assistant Exammer U Weldon [73] Assignee: ARPInstruments, Inc., Newton [57] ABSTRACT Upper Fans Mass- In anelectronic musical instrument of the type includ- 22 Fiied; July 11,1973 ing a keyboard and a resistor voltage divider having points therealong respectively coupled by way of ac- [21] Appl' 378350 tuable keysassociated with the keyboard to a single R l t d U A li i D output bus,there is provided improved control elec- [63] continuatiommpan of SenN0. 220 914 Jan 26 tronics having output signals that control, forexample,

1972 abandoned an envelope generator and a voltage controlledOSClllator. The control electronics includes an oscillator 52 us. (:1.84/1.01, 84/124 and gate circuit Coupled to the bus for Providing a 51Int. Cl. G101: 1/00 gate Output Signal which is Pramt as long as atleast 58 Field of Search 84/1.01, 1.13 1.24 1.26 one key is actuated, aSample/had circuit Coupled to 84/DIG 7 D16 8 i the'bus for providing acontrol voltage signal the amplitude of which is a function of theposition of the ac- [56] References Cited tuated key, and a triggersignal means coupled to the keyboard and responsive to the gate circuitand the UNITED STATES PATENTS actuation of two or more keys forproviding a trigger 3,288,904 11/1966 George 84/1.01 Signal of Shorterduration than the gate Signal and 22:32: curring near the commencementof the gate signal. 3:609:203 9/1971 Adachi 84/101 25 Claims, 8 DrawingFigures T p CONTROL v. 0.0. V.C.F. V.C.A. 1 OUTPUT KEYBOARD 80 ANDCONTROL VOLTAGE CIRCUIT P2 DIVIDER GATE BUS ENVELOPE 20 TRIGGER 1GENERATOR /2 4 PAIENIEIIIIII: 6I9Z4 SHEET 1 BF 5 TOP cONTROL V.C.O.V.C.F. VOA. T T /4 E Q Z9 OU PU KEYBOARD 90 AND CONTROL VOLTAGE CIRCUITPl P2 DIVIDER GATE BUS/ V ENVELOPE 20 TR GGER GENERATOR /2 40 F/G.

CURRENT SOURCE 0 I IP E TRIGGER THRESHOLD R SEP E AND AMPLIFIER CIRCUITCIRCUIT \/|BRATOR CIRCUIT & 2 TOP I I I B /7 /& KEYBOARD /4 A B lTRIGGER AND OUTPUT VOLTAGE BUS VOLTAGE FET-CAPACITOR OUTPUT DIVIDERFOLLOWER HOLD CIRCUIT Fol-LOWER CONTROL I 2 g5 3 6 VOLTAGE Q OUTPUTOscILLATOR GATE F/G 3 7 cIRcuIT /9 22 GATE OUTPUT TOP BUS O I s s s s ss I I" I I R .5 i- L-& A. {l I009 CONTROL CIRCUITRY FOR ELECTRONICMUSICAL INSTRUMENT RELATED APPLICATION This is a continuation-in-part ofU.S. Pat. application Ser. No. 220,914 filed Jan. 26, 1972 nowabandoned.

FIELD OF THE INVENTION The present invention relates in general to anelectronic musical instrument preferably of the keyboard type. Moreparticularly, the present invention is directed to a new and improvedcontrol circuit for an electronic musical instrument. The presentinvention preferably employs a single bus which couples from anassociated voltage divider means of the keyboard to the controlcircuitry, and the control circuitry includes means for providing a gatesignal, a trigger signal, and a control voltage signal. These signalsmay couple to other conventional utilization circuits such as a voltagecontrolled oscillator or envelope generator.

BACKGROUND OF THE INVENTION In known electronic musical instruments thecontrol circuitry is usually coupled from at least two bus linesassociated with the keyboard of the instrument. Each bus in turn has avoltage divider associated therewith. The voltages impressed on each busare selectively coupled, upon actuation of the key or keys of thekeyboard, to the control circuitry and the control circuitry includesmeans coupled to one bus for providing a gate signal and second meanscoupled to the other bus for providing a trigger signal. Onedisadvantage to this prior art scheme is that additional circuitry isneeded to provide the two bus output. This also means that two voltagedividers have to be used. In the present invention, preferably a singlebus is employed and is coupled from a single voltage divider to thecontrol circuitry of the present invention.

Known control circuitry also has certain other disadvantages associatedtherewith such as not providing sufficient noise and switch bounceimmunity, not providing an accurate control voltage signal, and aninaccurate time relationship between the gate, trigger, and controlvoltage signals. These and other disadvantages of the prior controlcircuits are believed to be overcome by the circuitry of the presentinvention.

OBJECTS OF THE INVENTION Accordingly, one important object of thepresent invention is to provide improved control circuitry for use in anelectronic musical instrument preferably of the keyboard type.

Another object of the present invention is to provide improved controlcircuitry as set forth in the preceding object and employing preferablya single bus coupled from the keyboard to the control circuitry.

A further object of the present invention is to provide a musicalinstrument having improved control circuitry as set forth in thepreceding objects, that may be constructed relatively inexpensively,that is not unnecessarily complex, and that is characterized by otheradditional features set forth hereinafter.

SUMMARY OF THE INVENTION To accomplish the foregoing and other objectsof the invention, the electronic musical instrument is characterized byimproved control circuitry preferably employing a single bus couplingfrom the keyboard to the control circuitry. The keyboard has meansassociated therewith for generating a signal, preferably of a voltageamplitude, corresponding to an actuated key of the keyboard, and asecond signal or voltage level change indicative of the actuation of atleast two keys or the release of at least one key. The control circuitryof this invention generally comprises gate signal means which mayinclude an oscillator and gate circuit, sample/hold means forestablishing a control voltage proportional to the voltage of the buscoupled from the keyboard, and trigger signal means preferably includingan amplifier, trigger circuit, and threshold circuit.

One feature of the present invention is the novel sample/hold circuit.This sample/hold circuit preferably includes a pair of field effecttransistors (FETs) and an output voltage follower.

Other features of the present invention reside in the use of anoscillator circuit as part of the gate signal means and in the use of athreshold circuit and multivibrator delay circuit as part of the triggersignal means.

BRIEF DESCRIPTION OF THE DRAWINGS Other objects, features and advantagesof the present invention should now become apparent upon a reading ofthe following detailed description when read in conjunction with thefollowing drawings in which:

FIG. 1 is a block diagram of an electronic musical instrument embodyingthe control circuitry of the present invention;

FIG. 2 shows a number of waveforms that are associated with the blockdiagram of FIG. 1;

FIG. 3 shows a block diagram of a preferred embodiment for the controlcircuitry of the present invention;

FIG. 4 shows a detailed circuit schematic diagram of the keyboard andvoltage divider of FIG. 3;

FIG. 5 shows a circuit diagram of a portion of the control circuitry ofthe present invention including the gate signal means and thesample/hold means;

FIG. 6 shows a circuit diagram of the remainder of the control circuitryof the present invention including the trigger signal means;

FIG. 7 shows various waveforms associated with the circuitry of FIGS. 5and 6; and

FIG. 8 is a circuit diagram for the envelope generator of FIG. 1.

DETAILED DESCRIPTION Referring now to the drawings and in particular toFIG. 1, there is shown a block diagram of an electronic musical systememploying the improved control circuit of the present invention andassociated single bus which is coupled from the keyboard to the controlcircuit.

The system of FIG. 1 in general comprises a keyboard and voltage divider10, control circuit 20, envelope generator 40, voltage controlledoscillator (V.C.O.) 50, voltage controlled filter (V.C.F.) 60, voltagecontrolled amplifier (V.C.A.) 70, and output speaker 80. Most of theblocks shown in FIG. 1 may be of conventional design with the exception,of course, of control circuit 20. The keyboard and voltage divider 10 isshown in more detail in FIG. 4 and includes a resistor voltage dividerand associated key actuated switches for coupling respective voltagelevels to the bus line 12. Keyboard and voltage divider may be ofconventional design and preferably includes a second output line 14coupled from a top end of the resistor voltage divider to controlcircuit 20. When a key of the keyboard is depressed a correspondingvoltage is coupled via line 12 to control circuit 20. When at least twokeys are depressed or a key is released with another being held, a levelchange occurs on output line 14, as discussed in more detailhereinafter.

Control circuit 20 generates a control voltage signal having a voltagelevel at any given time which is proportional to the position of the keythat is actuated. The purpose of the control voltage signal is tocontrol the frequency of V.C.O. 50. A typical control signal is shown inFIG. 2C for one particular predetermined sequence of key actuations.

Control circuit 20 also generates a gate signal and a trigger signalboth of which are coupled to envelope generator 40 which may be ofconventional design. A

gate signal is shown in FIG. 2A. The gate signal is at its high statewhen a key is depressed and remains in this state as long as at leastone key remains depressed. The gate signal controls the output ofenvelope generator 40 and generally sustains the signal transfer throughanother device such as voltage controlled filter 60.

FIG. 2B shows a trigger signal that may be generated by control circuit20 and which is coupled to envelope generator 40 to initiate the attackof the note by the envelope generator. The trigger signal preferablycommences at about the same time the gate signal goes high, or slightlythereafter, and as shown in FIG. 2B, has a width of about 100microseconds and an amplitude of +15 volts. The trigger signal appearsmomentarily at the start of each key depression.

Atypical output of envelope generator 40 is depicted in FIG. 2D and theparticular waveform shown is controlled by the gate and trigger signalsof shown in FIG. 1. The attack time, initial decay time, and releasetime of the envelope generator output waveform may be conventionallycontrolled by RC time constant networks or the like of generator 40. Theoutput waveform shown in FIG. 2D is coupled through potentiometers P1and P2, to voltage controlled filter 60 and voltage controlled amplifier70, respectively, to control the outputs from these two devices. Theoutput of voltage controlled amplifier 70 then couples to outputloudspeaker 80 in a conventional manner.

Referring now to FIG. 3, there is shown a block diagram of a preferredembodiment of the control circuit of FIG. 1. Control circuit 20generally includes keyboard and voltage divider 10 having bus 12 andcurrent source 15 associated therewith, gate signal means 16, triggersignal means 17, and control voltage signal means 18. A circuitschematic diagram of the keyboard and voltage divider 10 is shown indetail in FIG. 4, and includes an output bus 12 which couples to thegate signal means 16 and the control voltage signal means 18.

The keyboard and voltage divider 10 also includes an output line 14taken at the top of the voltage resistor string and which couples to thetrigger signal means 17.

The gate signal means includes an oscillator 19 and a gate circuit 22.Oscillator 19 is free-running prior to depression of a key of thekeyboard, and the output of oscillator 19 does not energize gate circuit22. When one of the keys of the keyboard is depressed the voltageimpressed on bus 12 causes oscillator 19 to stop oscillating. Thisaction causes the gate circuit 22 to be en abled and a gate outputsignal, such as the one shown in FIG. 7B commences. In FIG. 7B thissignal is shown as rising to a positive level at a predetermined timeconstant upon depression of the key and reverting negatively when thekey is released. The gate circuit 22 also generates an A output upondepression of the key as shown in FIG. 7A. This A output is a positivegoing pulse that is coupled to trigger signal means 17 for generating atrigger output signal as discussed hereinafter. The gate circuit 22 alsogenerates a C output which is coupled to control voltage signal means 18and to trigger signal means 17. The C output signal is shown in FIG. 7Cand is similar to the gate output signal of FIG. 7B but has a differentamplitude swing.

Trigger signal means 17 shown in FIG. 3 generally include an AC coupledamplifier 24, a trigger circuit 25, a threshold circuit 26, a monostablemultivibrator 28, and an AND circuit 29. As previously indicated when atleast two keys are depressed, or a key is released with another beingheld, the total voltage across the voltage divider string changes and avoltage fluctuation is AC coupled from output line 14 to amplifier 24.FIG. 7D indicates the waveform at the output of amplifier 24 which showsa positive spike when the key is depressed and a negative spike when itis released. Trigger circuit 25 may be a full wave rectifier typecircuit and also receives an input signal, namely signal A, from gatecircuit 22 for enabling trigger circuit 25. The B output shown in FIG.7E is a typical trigger output from trigger circuit 25 and couples tocontrol voltage signal means 18. The output of trigger circuit 25couples to threshold circuit 26 which is only responsive to a pulse of apredetermined amplitude, such as the pulse shown in FIG. 7F, in order toset monostable multivibrator 28. Monostable multivibrator 28 delays thetrigger pulse from trigger circuit 25 to assume that a trigger outputsignal is generated only when the gate output signal is still present,and the output of multivibrator 28 is coupled to AND circuit 29. If theC output is still high the AND circuit 29 generates a trigger outputsignal as indicated in FIG. 7H, for example. The trigger output signalis shown as having a relatively narrow pulse width and commences afterthe beginning of the gate output signal with the delay being determinedby the multivibrator 28.

The control voltage signal means 18 shown in FIG. 3 generally comprisesa voltage follower 32, an FET- capacitor hold circuit 34 and an outputfollower 36. The voltage follower 32 is coupled to bus 12 and isresponsive to the voltage impressed thereon for coupling a signal tocircuit 34. The circuit 34 is responsive to both the B and C signals forcontrolling the charging of a sample capacitor. The B signal controlsthe charging of the capacitor by way of a fast charge FET and the Csignal sustains the capacitor charge via a second FET. The output of thecapacitor is sensed by output follower36 and the output of follower 36is a control voltage signal such as the one shown in FIG. 2C.

Referring now to FIG. 4 there is shown the keyboard and voltage divider10 of FIGS. 1 and 3. The keyboard includes a plurality of manuallyoperable switches S which are actuable to couple different voltages fromthe resistive voltage divider to bus 12. The resistive voltage dividercomprises a plurality of resistors Rconnected in series from the topoutput line 14 to ground.

The current source shown in FIG. 3 also couples to output line 14 andprovides a constant current for each of the resistors R. In oneembodiment each of these resistors is a 100 ohm resistor. When a singlekey is depressed the corresponding voltage from the voltage divider iscoupled to bus 12. When two or more keys are depressed the resistorstherebetween are shunted and the voltage on line 14 shifts negatively, avalue which is depended upon the positions of the actuated switches.When the switches are released, the output line 14 goes positive.

Referring now to FIGS. 5 and 6 there is shown a circuit diagram of thecontrol circuit of FIG. 3 showing, in particular, the gate signal means16, the trigger signal means 17 and the control voltage signal means 18.As previously indicated the gate signal means 16 comprises an oscillator19 and a gate circuit 22.

Oscillator 19 is a phase shift type oscillator and generally comprisesan amplifier section 21, a phase shift section 23, and an outputtransistor Q17. The input to oscillator 19 is coupled by way of couplingcapacitor C20 from bus 12 to the base of transistor Q16. The output ofoscillator 19 may be taken at the collector of transistor Q17 andcouples to an input transistor of gate circuit 22.

When there is no key depressed the bus 12 is essentially floating withthe exception of resistor R37 (high resistance), and transistors Q15 andQ16 of amplifier 21 are permitted to cyclically conduct at a preselectedfrequency of, for example, 200 KHZ. The amplifier 21 also includesresistors R49 and R50 which couple from the collectors of transistorsQ15 and Q16, respectively, to the +15 volt supply. Resistor R51 couplesfrom the emitter of transistor Q15 to the l 5 volt supply. CapacitorsC21, C22, and C23 are coupling capacitors.

The phase shifter network 23 includes three filter sections includingresistors R53-R55 and capacitors C24-C26. A feedback connectionincluding capacitor C27 and resistor R56 is coupled from the collectorof transistor Q15 to the base of transistor Q17. The three sectionfilter network 23 provides an essentially 180 phase shift thus providingthe regenerative feedback for oscillator 19. While the oscillator isoscillating, transistor Q17 cyclically conducts and a current isprovided by way of resistor R57 to capacitor C28 of gate circuit 22thereby causing capacitor C28 to charge, holding transistor 018 on.

When one of the keys of the keyboard is depressed, a relatively lowimpedance to ground on the order of hundreds of ohms is coupled by wayof capacitor C20 to transistor Q16 holding transistors Q16 and Q15 offand preventing further oscillation of oscillator 19. When this actionoccurs, transistor 017 receives insufficient base current and is nolonger conductive. Capacitor C28 discharges causing transistor 018 toeventually turn off.

In addition to transistor Q18 the gate circuit 22 also includestransistor Q19. As previously indicated resistor R57 couples from thecollector of transistor Q17 by way of resistor R59 to the base oftransistor Q18. Resistor R58 couples from the junction between resistorsR57 and R59 to the l5 volt supply and has capacitor C28 connected inparallel thereacross. Both transistors Q18 and Q19 have resistors R60and R61 connected from their collectors, respectively, to the +15 voltsupply. The collector of transistor 018 also couples to the base oftransistor 019, by way of resistor R63 to the l 5 volt supply, and byway of capacitor C29 and resistor R62 also to the -15 volt supply. Theemitter of transistor Q19 couples to the C output and also by way ofdiode CR12 to the gate output. The gate output includes a terminatingresistor R65 coupled to ground. The A output is taken between resistorR62 and capacitor C29.

When oscillator 19 is oscillating and transistor 018 is conductive,capacitor C29 is charged and the A output is at essentially -15 volts(see FIG. 7A). At that time the conduction of transistor Q18 preventstransistor Q19 from conducting, the gate output is essentially at groundand the C output is at l5 volts (see FIGS. 78 and 7C). When theoscillator ceases oscillating transistor Q18 turns off fairly rapidlyand as the charge across capacitor C29 cannot instantaneously change,the voltage at point A goes to 12 volts causing transistor Q19 toconduct. This action causes the gate output signal to reverse from aground level to a +10 volt level with a time constant of about 2milliseconds as determined at least in part by capacitor C29 andresistors R60 and R63. Similarly, the C output goes from 15 volts to+10, approximately. When the key is released transistor Q19 turns offfarily rapidly and the gate signal reverts to ground in about 0.1milliseconds.

Referring now to FIG. 6 there is shown a circuit diagram of the triggersignal means 17 which generally comprises amplifier 24, trigger circuit25, threshold circuit 26, multivibrator 28, and AND circuit 29. Theoutput line 14 of keyboard and voltage divider 10 couples by way ofcapacitor C2 and resistor R5 to the negative input of operationalamplifier Al. The positive input of amplifier Al is grounded. Aspreviously indicated, when two or more keys are depressed the voltage online 14 decreases slightly, and when a key is released with anotherbeing held the voltage on line 14 increases.

FIG. 6 also shows the current source 15 which gener- .ally comprisestransistor Q1 and associated resistors.

Resistors R1 and R2 and diode CR1 couple in series from the +15 voltsupply to ground and establish a bias for the base of transistor Q1.Resistor R4 and potentiometer P3 couple in series from the emitter oftransistor O1 to the +15 volt supply, and potentiometer P3 may be usedfor varying the constant current at the collector of transistor Q1,which current is coupled by way of output line 14 to the resistivevoltage divider of FIG. 4.

The fluctuations on output line 14 are AC coupled to the negative inputof amplifier Al, and amplifier A1 may be a conventional operationalamplifier. The amplifier A1 has, coupled between its input and output, apair of oppositely poled diodes CR2 and CR3 which prevent saturation ofamplifier Al and enable a faster operation of the amplifier. Resistor R6is coupled in series with resistor R7 between the input and output ofamplifier Al and resistor R6 together with resistor R5 define the ACgain of the amplifier which is on the order of 30 in one particularembodiment. Capacitor C4 which also couples between the input and outputof amplifier A1 stabilizes the operation of the amplifier. The DC gainof the amplifier is controlled by resistors R7 and R8 and the output ofthe amplifier is limited to a. or 9 volts. Normally, when no key isbeing depressed the output of amplifier A1 is at approximately ground.When two or more keys are depressed the output of amplifier A1 is shownin FIG. 7D as a positive impulse, and when a key is released FIG. 7Dshows the negative impulse that occurs at the output which is coupled totrigger citcuit 25 by way of capacitor C5.

The trigger citcuit 25 generally comprises transistors Q2, Q3 and Q4.Transistor Q2 is normally (no key depressed) biased by resistors R9-R12and is in the active operating area. Resistors R9 and R provide a biasvoltage of approximately -7.5 volts for the base of transistor Q2. Thus,when a positive pulse is coupled by way of capacitor C5 from amplifierA1, transistor Q2 tends to conduct harder. Alternatively, when anegative pulse is coupled to the base of transistor Q2 it tends toconduct less current between its emitter and collector.

The collector of transistor Q2 couples by way of capacitor C6 and diodeCR4 to the base of transistor Q4. Similarly, the emitter of transistorQ2 is coupled by way of capacitor C7 and diode CR5 to the base oftransistor Q4. When transistor Q2 is normally biased both diodes CR4 andCR5 are back-biased and transistor Q4 is nonconducting. As indicated inFIG. 7E, the B output is then at l5 volts. The B output is taken at thecollector of transistor Q4. When transistor O2 is caused to change itsconduction and, for example, conducts more current the collector voltagedecreases, diode CR4 instantaneously conducts, and transistor Q4 alsoconducts via capacitor C8 providing a positive pulse at the B output ofapproximately volts. Similarly, when transistor Q2 decreases inconduction diode CR5 conducts, transistor Q4 conducts and a similar Boutput is generated at the collector of transistor Q4.

As previously indicated with reference to FIG. 3 the trigger circuitalso produces a B output when only a single key is depressed by means ofthe A output signal from gate circuit 22. For this purpose the triggercircuit 25 comprises transistor Q3 whose collector couples by way ofresistor R16 and resistor R66 to the base of transistor Q4, whoseemitter is coupled to 1 5 volts, and whose base couples by way ofresistor R18 from the A output of gate circuit 22. A diode CR6 alsocouples from the base to emitter of transistor Q3 and protectsthetransistorfrom excess negative voltages which may occur upon release ofa key when the A output goes as negative as possibly to volts.

When the A signal goes from -15 to -12 volts, transistor O3 is caused toinstantaneously conduct thereby causing a momentary conduction oftransistor Q4 and the generation of a B output pulse like the one shownin FIG. 7E.

The collector of transistor Q4 (B output signal) couples to thresholdcircuit 26 which comprises transistors Q5 and Q6. Transistor Q5 has itscollector coupled by way of resistor R22 to to the +l5 volt supply andalso couples by way of storage capacitor C10 to ground. A

diode CR7 couples between the emitter and base of transistor Q5 and isused to protect the transistor against negative impulses. Resistors R20and R21 connect in series between ground and the emitter of transistorQ5 and the junction between these resistors cou ples to the emitter oftransistor Q6. Resistors R23 and R24 which are of equal value bias thebase of transistor Q6 to approximately +7.5 volts. Resistors R23 and R24establish a threshold level which may be varied by making one resistorvariable. The output of the threshold circuit may be taken at thecollector of transistor Q6.

When a B output signal occurs transistor Q5 conducts and capacitor C10which was previously charged by way of resistor R22 discharges rapidlythrough transistor Q5 causing a positive pulse at the emitter oftransistor Q6. The resistors R20 and R21 provide a voltage divider andif the B output pulse is a true pulse, and not a noise pulse possiblycaused by switch bounce, the pulse at the emitter of transistor Q6should be on the order of +10 volts in maximum amplitude. With the baseof transistor Q6 at +7.5 volts transistor Q6 will conduct and an outputsignal is coupled to multivibrator 28. If the pulse at the emitter oftransistor 06 is not sufficiently positive, transistor Q6 will notconduct and a trigger output signal will not be subsequently generated.The effects of contact bounce are minimized by requiring capacitor C10to be charged to produce the trigger pulse, and by the +7.5 voltthreshold required to turn on transistor Q6.

FIG. 6 also shows the monostable multivibrator 28 which is ofconventional design and includes transistors Q7 and Q8 along withapproximate biasing resistors and timing capacitor C12. In its unexcitedstate the multivibrator 28 has transistorQ7 off and transistor Q8conducting with its output emitter at approximately ground. Whentransistor Q6 conducts transistor Q7 also goes into conductiontemporarily and transistor Q8 automatically turns off with its emitterreverting to a positive voltage. The on time or delay time provided bymultivibrator 28 is controlled by capacitor C12 and resistors R25 andR26. After this'delay has elapsed transistor Q8 automatically conductsand its emitter goes back to ground. It is this ground-going signal thatis coupled by way of capacitor C13 to the base of transistor Q9 whichcauses conduction of transistor Q9, but only if transistor Q10 is alsoconducting.

The AND circuit 29 comprises transistors Q10 and Q11. Transistor Q11 hasits emitter coupled to ground and its base coupled by way of resistorR34 from the C output of gate circuit 22. Resistor R35 couples from thebase to the emitter of transistor Q11, and resistors R33 and R32 couplein series from the collector of k transistor Q11 to the +l 5 voltsupply. The base of transistor Q10 connects intermediate resistor R32and R33. Transistor Q10 provides a conduction path for transistor Q9 butonly when transistor Q10 is conducting. Transistor Q10 will beconducting when the C output is present and transistor Q11 is thusconducting. For this condition the base of transistor Q10 is morenegative than the emitter and transistor Q10 is on. If the C output isnot present transistor Q10 remains off and a trigger signal on thetrigger output line will not be generated by way of resistor R36. Atypical trigger output Referring again to FIG. 5 there is shown thecontrol voltage signal means 18 which generally comprises voltagefollower 32, FET capacitor hold circuit 34, and output follower 36. Thevoltage follower 32 includes operational amplifier A2 which may be ofconventional design and has its positive input coupled by way of re- 1sistor R38 from bus 12. The input voltage on bus 12 which occurs whenone or more keys are depressed is coupled by way of resistor R38 andcapacitor C14 which together form a low pass filter. Amplifier A2 has acapacitor C 16 coupled between its negative input and its output forstabilizing amplifier A2. The amplifier A2 is designed with unity gainand its output is coupled by way of resistors R40 and R41, and alsoportamento potentiometer P4 to circuit 34.

The FET capacitor hold circuit 34 generally comprises FET transistorsQ12 and Q13 and sample capacitor C17. Resistor R41 couples to the gateof transistor Q12 and resistor 40 couples to the gate of transistor Q13.The gates of transistor Q12 and Q13 also couple by way of diodes CR8 andCR9 to the C and B outputs, respectively. The sources (S) of transistorsQ12 and Q13 couple together to potentiometer P4. The drain of transistorQ13 couples directly to capacitor C17 and the drain of transistor Q12couples by way of high impedance resistance R42 to capacitor C17. Theoutput of circuit 34 may be considered as taken at the ungrounded sideof capacitor C17.

Circuit 34 also includes resistors R43 and R45 which are coupled inseries between the cathode of diode DR9 and the B input from triggercircuit 25. Resistor R44 couples from the cathode of diode CR9 to the Ivolt supply and capacitor C18 couples to ground providing a slight delayof the B input pulse.

When a single key is depressed, the A signal is generated, the B outputtrigger is coupled to the cathode of diode CR9, and the output ofamplifier A2, which is positive, is coupled by way of resistor R40,potentiometer P4, and FET 13 to cause a rapid charging of capacitor C17to a voltage level corresponding to the voltage on bus 12. Theportamento potentiometer P4 provides a variable time constant for theFET charging if this is desired. An ON-OFF switch may be associated withpotentiometer P4 for including this feature or not. The C signal whichis coupled to the cathode of diode CR8 keeps transistor Q12 on providinga trickle charge for capacitor C17 even after the B output pulse hasterminated. Resistor R42 which is in series with capacitor C17 and FETtransistor Q12 provides a slight lag so that the sudden change in theoutput of amplifier A2 upon release of a key does not affect the voltageacross capacitor C17 before the decrease of the C output sig nal whichshuts off transistor Q12. In addition, a diode CR prevents a B outputsignal from turning on transistor Q13 unless a gate signal is present.This feature adds further contact bounce immunity to the circuitry.

The output follower 36 includes a dual FET pair Q14 and amplifier A3which may be a differential or operational amplifier. In the embodimentshown amplifier A3 operates as a differential amplifier and has a firstinput coupled from the source of transistor Q14A and a second inputcoupled from the source of transistor Q14B. The drain electrodes of bothtransistors 014A and 0143 couple to the +15 volt supply. The gateelectrode of transistor Q14A couples to capacitor C17 and the gateelectrode of transistor Q14B couples to shield SI-I. The shield alsocouples by way of line 36A to the control voltage output terminal. Byproviding a feedback Ii'ne 36A there should ideally be no current in theshield SI-I, thus stabilizing the voltage across capacitor C17.

Amplifier A3 receives a voltage from capacitor C17 and couples thissignal from its output by way of resistor R48 to the control voltageoutput terminal. A typical control voltage is shown in FIG. 2C for apredetermined series of key depressions.

FIG. 8 shows one circuit diagram of an envelope generator that may beemployed in the block diagram of FIG. 1. As previously indicated, thisenvelope generator receives a gate input signal as shown in FIG. 2A anda trigger input signal as shown in FIG. 2B and generates an outputcontrol waveform as shown in FIG. 2D. The gate signal controls theinitiation of the attack and also the initiation of the release asdepicted in FIG. 2, and the trigger signal, especially one that does notoccur initially but occurs during the gate signal, controls additionalattack-decay peaks.

In FIG. 8 the gate signal couples to diode CR15 and also to transistorQ20. The trigger signal couples via capacitor C32 to a bistable latchcircuit including transistors Q27 and Q28. The output from the circuitFIG. 8 is tekan by way of resistor R from the collector of transistorQ24.

When the gate signal goes high diode (CRIS) is forward-biased, diodeCR14 is reversed-biased and a charging current is provided by way ofpotentiometer P5 and diode CR13 to integrating capacitor C30.

The trigger signal also goes positive at the same time approximatelythat the gate signal goes positive. This signal is coupled by way ofcapacitor C32 to the base of transistor Q28 causing that transistor toconduct. This action also causes transistor Q27 to conduct therebyproviding the initial attack current by way of potentiometer P5 anddiode CR13 to capacitor C30. When the trigger signal ends thetransistors Q27 and Q28 remain conductive by the feedback path includingdiode CR23.

Thus the capacitor C30 is permitted to charge at a rate determined inpart by potentiometer P5. As capacitor C30 charges the voltage at theemitter of transistor Q25 exponentially increases. When the voltage atthe emitter of transistor Q25 exceeds the threshold voltage set at thebase of transistor Q25, that transistor conducts thereby terminating theattack time interval. When transistor Q25 conducts transistor Q26 alsoconducts thereby causing the bistable latch circuit to reset. In otherwords, transistors Q27 and Q28 cease conduction. The initial attackcurrent to potentiometer P5 then stops and the voltage across capacitorC30 no longer increases. The voltage across capacitor C30 then decaysthrough diode CR16 potentiometer P8 and transistor Q21. The rate ofdecay of the voltage across capacitor C30 is controlled primarily by thesetting of potentiometer P8. When this voltage has decayed sufficientlytransistor Q21 stops conduction and the sustain interval commenceswherein the voltage across capacitor C30 is maintained at apredetermined voltage as set by potentiometer P7 which couples to thebase of transistor Q21.

When the gate signal reverts back to its low level, capacitor C30 ispermitted to continue its discharge by way of diode CR14 andpotentiometer P6. Thus, potentiometer P6 controls the release timeconstant as depicted in FIG. 2D. When the gate signal goes to itslowlevel the output of transistor Q20 goes to its high level therebyturning on transistor Q26 and assuring that the bistable latch circuitis reset.

At this point, only the initial trigger signal has been considered. If atrigger signal occurs at a later point during the gate signal anotherattack peak is generated. This trigger signal causes the bistable latchcircuit to set again causing temporary attack current by way ofpotentiometer P and, thereafter, a decay current by way of potentiometerP8 until the voltage cross capacitor C30 reverts to its previous sustainlevel as set by poten tiometer P7.

From the foregoing it can be seen that the output voltage coupled fromthe collector of transistor Q24 is a waveform of the type shown in FIG.2D.

Having described one embodiment of the present invention otherembodiments and modifications thereof are contemplated as falling withinthe spirit and scope of the present invention. The invention is thus tobe limited only by the appended claims.

What is claimed is: 1. in an electronic musical instrument of the typehaving keyboard means including a keyboard, means for providing a firstsignal coupled from the keyboard the amplitude of which corresponds tothe actuated key, and means for providing a second signal coupled fromthe keyboard indicative of the actuation of at least two keys or therelease of a key, control circuitry coupled from the means for providingthe first and second, signals and comprising, in combination:

first circuit means coupled from said first signal providing means forproviding a gating signal which is present as long as at least one keyis actuated;

second circuit means including delay means and coupled from said secondsignal providing means for providing a triggering signal which isgenerally of shorter duration than the gating signal and is present atabout the commencement of the gating signal;

sample and hold means coupled from said first signal providing means andenabled by the gating signal derived from said first circuit means forestablishing a control signal proportional to the first signal,

and means coupled from said second circuit means for controllingoperationof said sample and hold means.

2. The circuitry of claim 1 wherein said keyboard circuitry includes avoltage divider having a plurality of resistors coupled in series and acurrent source feeding the voltage divider,

said first signal being coupled from said voltage divider at a pointcorresponding to the actuated key,

and said second signal being coupled from an end of said voltagedivider.

3. The circuitry of claim 2 wherein said keyboard has a number of keyactuated switches and said keyboard and voltage divider are arrangedwith each key actuated switch coupled to a corresponding resistor of thevoltage divider so that actuation of two keys bypasses the associatedresistors therebetween causing said second signal to decrease, andreleasing a key causes said second signal to increase.

4. The circuitry of claim 1 wherein said first circuit means comprisesan oscillator and a gate circuit for generating a gate pulse upon theactuation of at least one key which is coupled to the second circuitmeans for providing the triggering signal when one key is actuated, andwherein said oscillator couples from said first signal providing meansto said gate circuit.

5. The circuitry of claim 4 wherein said oscillator includes anamplifier section and a phase shift section, said oscillator includingmeans defining a low impedance path for inhibiting said amplifiersection to stop oscillator operation upon actuation of a key.

6. The circuitry of claim 4 wherein said sample and hold means includesa capacitorcharge network and means copuling said gating signal to saidcapacitor charge network to provide a charging current thereto for theapproximate duration of the gating signal.

7. The circuitry of claim 6 wherein said charging current is a holdingcurrent.

8. The circuitry of claim 1 wherein said second circuit means comprisesan AC coupled amplifier coupled from the second signal providing means,and a trigger circuit coupled from the AC coupled amplifier andresponsive to actuation of at least two keys or the release of a key toprovide the triggering signal.

9. The circuitry of claim 8 wherein said first circuit means comprises agate circuit for generating a gate pulse upon the actuation of a key,said trigger circuit comprises an input circuit for receiving said gatepulse for providing the triggering signal when one key is actuated.

10. The circuitry of claim 9 wherein said trigger circuit comprises aphase splitter network and an output transistor which is conductive when.the output of the AC coupled amplifier goes positive or negative from apredetermined reference level.

11. The circuitry of claim 1 wherein said second circuit means includesa trigger circuit coupled from the second signal providing means forproviding the triggering signal and said first circuit means comprises agate circuit for generating a gate impulse, said trigger circuit alsoincluding means responsive to the gate impulse for providing thetriggering signal.

12. The circuitry of claim 11 wherein said sample and hold meansincludes a capacitor charge network and means coupling said triggeringsignal to said capacitor charge network to provide an initial chargingcurrent thereto for the duration of the triggering signal.

13. The circuitry of claim 12 comprising means coupling said gatingsignal to said capacitor charge network to provide a sustaining chargingcurrent thereto for the approximate duration of the gating signal.

14. The circuitry of claim 13 wherein said capacitor charge networkincludes a pair of transistors, one being controlled by the gatingsignal and the other being controlled by the triggering signal.

15. The circuitry of claim 14 wherein said transistors are field effecttransistors and comprising a capacitor having one side coupled to bothsaid transistors.

16. The circuitry of claim 1 wherein said second circuit means comprisesa trigger circuit coupled from the second signal providing means and athreshold circuit coupled from the trigger circuit and responsive to atriggering signal of a predetermined amplitude or greater for activatingthe threshold circuit.

17. The circuitry of claim 16 comprising a delay circuit coupled fromsaid threshold circuit for delaying the triggering signal.

18. The circuitry of claim 17 comprising an AND circuit coupled from thedelay circuit and the first circuit means for generating a triggeroutput signal when said 13 delayed triggering signal is present and saidgating signal is present.

19. The circuitry of claim 18 wherein said delay circuit includes amonostable multivibrator.

20. The circuitry of claim 16 wherein said threshold circuit includes atransistor and resistor means for biasing the control electrode of thetransistor at a fixed threshold level.

21. The circuitry of claim 1 wherein said sample and hold means includesan input voltage follower coupled from the first signal providing means,a capacitor charging network coupled from the voltage follower andresponsive to both the gating and triggering signals, and an outputfollower coupled from the capacitor charging network and having acontrol voltage output terminal.

22. The circuitry of claim 21 wherein said output follower includes apair of field effect transistors coupled from the capacitor chargingnetwork and a different circuit coupled from the transistors to theoutput terminal.

23. The circuitry of claim 1 wherein said sample and hold means includesa charging network coupled from the first signal providing means andincluding a capacitor means, and first and second field effecttransistors coupling from an input of the network to the capacitormeans, said first transistor having a control electrode responsive tosaid gating signal for controlling the conduction of said firsttransistor to sustain the charge on said capacitor means while a key isbeing actuated, said second transistor having a control electroderesponsive to said triggering signal for controlling the conduction ofsaid second transistor to initially quick charge said capacitor meansupon actuation of a key.

24. In an electronic musical instrument of the type having keyboardcircuitry including a keyboard means for providing a first signal theamplitude of which corresponds to the actuated key, and means forproviding a second signal indicative of the actuation of at least twokeys or the release of a key, control circuitry coupled from the meansfor providing the first and second signals and comprising, incombination;

a first circuit means coupled from said first signal providing means forproviding a gating signal;

a second circuit means coupled from said second signal providing meansfor providing a triggering signal which is generally shorter in durationthan the gating signal and is present at about the commencement of thegating signal;

third circuit means coupled from said first signal providing means forestablishing a control signal proportional to the first signal,

means coupled from said second circuit means for controlling operationof said third circuit means,

and means coupled from said first circuit means to said second circuitmeans for providing the triggering signal when one key is actuated.

25. The circuitry of claim 24 comprising means responsive to said gatingsignal for enabling the output of said second circuit means.

1. In an electronic musical instrument of the type having keyboard meansincluding a keyboard, means for providing a first signal coupled fromthe keyboard the amplitude of which corresponds to the actuated key, andmeans for providing a second signal coupled from the keyboard indicativeof the actuation of at least two keys or the release of a key, controlcircuitry coupled from the means for providing the first and second,signals and comprising, in combination: first circuit means coupled fromsaid first signal providing means for providing a gating signal which ispresent as long as at least one key is actuated; second circuit meansincluding delay means and coupled from said second signal providingmeans for providing a triggering signal which is generally of shorterduration than the gating signal and is present at about the commencementof the gating signal; sample and hold means coupled from said firstsignal providing means and enabled by the gating signal derived fromsaid first circuit means for establishing a control signal proportionalto the first signal, and means coupled from said second circuit meansfor controlling operation of said sample and hold means.
 2. Thecircuitry of claim 1 wherein said keyboard circuitry includes a voltagedivider having a plurality of resistors coupled in series and a currentsource feeding the voltage divider, said first signal being coupled fromsaid voltage divider at a point corresponding to the actuated key, andsaid second signal being coupled from an end of said voltage divider. 3.The circuitry of claim 2 wherein said keyboard has a number of keyactuated switches and said keyboard and voltage divider are arrangedwith each key actuated switch coupled to a corresponding resistor of thevoltage divider so that actuation of two keys bypasses the associatedresistors therebetween causing said second signal to decrease, andreleasing a key causes said second signal to increase.
 4. The circuitryof claim 1 wherein said first circuit means comprises an oscillator anda gate circuit for generating a gate pulse upon the actuation of atleast one key which is coupled to the second circuit means for providingthe triggering signal when one key is actuated, and wherein saidoscillator couples from said first signal providing means to said gatecircuit.
 5. The circuitry of claim 4 whereIn said oscillator includes anamplifier section and a phase shift section, said oscillator includingmeans defining a low impedance path for inhibiting said amplifiersection to stop oscillator operation upon actuation of a key.
 6. Thecircuitry of claim 4 wherein said sample and hold means includes acapacitor charge network and means copuling said gating signal to saidcapacitor charge network to provide a charging current thereto for theapproximate duration of the gating signal.
 7. The circuitry of claim 6wherein said charging current is a holding current.
 8. The circuitry ofclaim 1 wherein said second circuit means comprises an AC coupledamplifier coupled from the second signal providing means, and a triggercircuit coupled from the AC coupled amplifier and responsive toactuation of at least two keys or the release of a key to provide thetriggering signal.
 9. The circuitry of claim 8 wherein said firstcircuit means comprises a gate circuit for generating a gate pulse uponthe actuation of a key, said trigger circuit comprises an input circuitfor receiving said gate pulse for providing the triggering signal whenone key is actuated.
 10. The circuitry of claim 9 wherein said triggercircuit comprises a phase splitter network and an output transistorwhich is conductive when the output of the AC coupled amplifier goespositive or negative from a predetermined reference level.
 11. Thecircuitry of claim 1 wherein said second circuit means includes atrigger circuit coupled from the second signal providing means forproviding the triggering signal and said first circuit means comprises agate circuit for generating a gate impulse, said trigger circuit alsoincluding means responsive to the gate impulse for providing thetriggering signal.
 12. The circuitry of claim 11 wherein said sample andhold means includes a capacitor charge network and means coupling saidtriggering signal to said capacitor charge network to provide an initialcharging current thereto for the duration of the triggering signal. 13.The circuitry of claim 12 comprising means coupling said gating signalto said capacitor charge network to provide a sustaining chargingcurrent thereto for the approximate duration of the gating signal. 14.The circuitry of claim 13 wherein said capacitor charge network includesa pair of transistors, one being controlled by the gating signal and theother being controlled by the triggering signal.
 15. The circuitry ofclaim 14 wherein said transistors are field effect transistors andcomprising a capacitor having one side coupled to both said transistors.16. The circuitry of claim 1 wherein said second circuit means comprisesa trigger circuit coupled from the second signal providing means and athreshold circuit coupled from the trigger circuit and responsive to atriggering signal of a predetermined amplitude or greater for activatingthe threshold circuit.
 17. The circuitry of claim 16 comprising a delaycircuit coupled from said threshold circuit for delaying the triggeringsignal.
 18. The circuitry of claim 17 comprising an AND circuit coupledfrom the delay circuit and the first circuit means for generating atrigger output signal when said delayed triggering signal is present andsaid gating signal is present.
 19. The circuitry of claim 18 whereinsaid delay circuit includes a monostable multivibrator.
 20. Thecircuitry of claim 16 wherein said threshold circuit includes atransistor and resistor means for biasing the control electrode of thetransistor at a fixed threshold level.
 21. The circuitry of claim 1wherein said sample and hold means includes an input voltage followercoupled from the first signal providing means, a capacitor chargingnetwork coupled from the voltage follower and responsive to both thegating and triggering signals, and an output follower coupled from thecapacitor charging network and having a control voltage output terminal.22. The circuitry of claim 21 wherein saId output follower includes apair of field effect transistors coupled from the capacitor chargingnetwork and a different circuit coupled from the transistors to theoutput terminal.
 23. The circuitry of claim 1 wherein said sample andhold means includes a charging network coupled from the first signalproviding means and including a capacitor means, and first and secondfield effect transistors coupling from an input of the network to thecapacitor means, said first transistor having a control electroderesponsive to said gating signal for controlling the conduction of saidfirst transistor to sustain the charge on said capacitor means while akey is being actuated, said second transistor having a control electroderesponsive to said triggering signal for controlling the conduction ofsaid second transistor to initially quick charge said capacitor meansupon actuation of a key.
 24. In an electronic musical instrument of thetype having keyboard circuitry including a keyboard means for providinga first signal the amplitude of which corresponds to the actuated key,and means for providing a second signal indicative of the actuation ofat least two keys or the release of a key, control circuitry coupledfrom the means for providing the first and second signals andcomprising, in combination; a first circuit means coupled from saidfirst signal providing means for providing a gating signal; a secondcircuit means coupled from said second signal providing means forproviding a triggering signal which is generally shorter in durationthan the gating signal and is present at about the commencement of thegating signal; third circuit means coupled from said first signalproviding means for establishing a control signal proportional to thefirst signal, means coupled from said second circuit means forcontrolling operation of said third circuit means, and means coupledfrom said first circuit means to said second circuit means for providingthe triggering signal when one key is actuated.
 25. The circuitry ofclaim 24 comprising means responsive to said gating signal for enablingthe output of said second circuit means.